The invention relates to a high speed computing apparatus and more particularly to a concurrent architecture for signal and image processing which incorporated multiple processing units.
Signal processing algorithms operating with huge amounts of data require an extremely high processing throughput. A common way to achieve high throughput is to use arrays of processing elements in different configurations like SIMD (Single Instruction Multiple Data) or MIMD (Multiple Instructions Multiple Data). To the present, only a few designs have attempted to implement MIMD architectures in a single integrated circuit.
A MIMD architecture operating on signals and images requires a very efficient utilization of the internal resources for a high operation throughput. This requirement becomes even more severe for a single Input/Output port system.